Micro Vias Affect Reliability Testing
Microvias are an important design element of High Density Interconnect (HDI) circuit boards. They allow designers to increase signal routing density, reduce traces and lead lengths, and improve component packaging and placement. While these benefits are significant, it is important for PCB designers to understand the potential reliability risks associated with microvias, and how they can mitigate these issues through careful layout planning and fabrication process considerations.
The primary concern with micro vias is the impact of thermal cycling on plated interfaces such as between two stacked vias or a microvia and its target pad. In these conditions, the substrate expands more than the copper plating within the microvia, causing stress that may eventually cause the interface to fail. This can occur even with a relatively low number of thermal cycles. A number of different factors influence the likelihood of failure, including the dielectric material, aspect ratio, and copper plating.
To minimize the effects of this issue, it is critical that the metallization within microvias be as thin as possible. This can be accomplished through the use of a shim layer between the copper plating and the base of the via hole, or by using a smaller than normal etch depth. These changes reduce the amount of stress generated at the plated interfaces, and also help to eliminate the voiding that is sometimes associated with this type of failure.
How Do Micro Vias Affect Reliability Testing?
Another area of concern with microvias is the formation of latent defects during manufacturing and assembly. These defects are often attributed to a mismatch between the coefficient of thermal expansion (CTE) of the copper in the microvia and that of the surrounding dielectric materials. This mismatch can cause a number of problems, such as interfacial separation, barrel cracks, corner/knee cracks, and target pad cracks.
The most common causes of these issues are poor design practices, improper PCB stack-up configurations, and poor manufacturing process control. To prevent these problems, it is essential that PCB designers follow IPC-T-50M guidelines and IPC-2226 standards when designing their PCBs, as well as carefully evaluate their stack-up designs with a fabricator prior to the initiation of manufacturing. Additionally, continuous resistance monitoring during reflow can be used to identify potential latent defect mechanisms.
Microvias find widespread application in various electronic devices across numerous industries. One of their primary uses is in mobile devices such as smartphones and tablets, where space constraints are paramount, and high-density interconnects are essential. By employing microvias, manufacturers can achieve greater functionality and performance in smaller form factors, contributing to the sleek designs and compactness of modern gadgets.
Other factors that can contribute to microvia failure are excessive voiding, the size of the buried via hole, and the presence or absence of copper wrap plating. However, a correlation between the volume void fraction and the aspect ratio of the microvia cannot be established, as these factors vary significantly between different types of vias.